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公司做网站怎么推广,百度教育app,做视频链接网站,公司网站建设费计入什么科目Memory-partition是在进行内存寻址进行读或者写数据的时候，我们寻找地址一般是全部比较一遍，但是我们可以就是先比较第一位，然后在比较接下来的位数。这样就减少了近一般的内存访问次数，大大降低了功耗。在这里，我定…

Memory-partition是在进行内存寻址进行读或者写数据的时候，我们寻找地址一般是全部比较一遍，但是我们可以就是先比较第一位，然后在比较接下来的位数。这样就减少了近一般的内存访问次数，大大降低了功耗。

在这里，我定义了地址空间为十六，字长也为十六的内存mem。这个内存是有读和写的功能。首先向内存mem中写入数据，然后再读数据。我们的memory-partition主要是在寻址的时候通过分成两段来减少动态功耗。

有memory-partition的代码：

module memory2(
clr, //reset
clk, //clock
address, //address for read or write
read_en, //read enable
write_en, //写使能
read_data, //读使能
write_data //读的数据
);

input wire clr; //reset
input wire clk; //clock
input wire [3:0]address; //address for read or write
input wire read_en; //read_enable signal
input wire write_en; //write_enable signal
output reg [15:0]read_data; //the data you read from the memory
input wire [15:0]write_data; //write data to memory

reg [15:0]mem[15:0]; //get a 16*16's memory

always@(posedge clr,posedge clk)
begin
if(clr)
begin
mem[0] <= 16'b0;
mem[1] <= 16'b0;
mem[2] <= 16'b0;
mem[3] <= 16'b0;
mem[4] <= 16'b0;
mem[5] <= 16'b0;
mem[6] <= 16'b0;
mem[7] <= 16'b0;
mem[8] <= 16'b0;
mem[9] <= 16'b0;
mem[10] <= 16'b0;
mem[11] <= 16'b0;
mem[12] <= 16'b0;
mem[13] <= 16'b0;
mem[14] <= 16'b0;
mem[15] <= 16'b0;
end
else if(write_en == 1'b1)
begin
if(address[3] == 1'b0)
begin
if(address[2:0] == 3'b000)
mem[0] <= write_data;
else if(address[2:0] == 3'b001)
mem[1] <= write_data;
else if(address[2:0] == 3'b010)
mem[2] <= write_data;
else if(address[2:0] == 3'b011)
mem[3] <= write_data;
else if(address[2:0] == 3'b100)
mem[4] <= write_data;
else if(address[2:0] == 3'b101)
mem[5] <= write_data;
else if(address[2:0] == 3'b110)
mem[6] <= write_data;
else if(address[2:0] == 3'b111)
mem[7] <= write_data;
end
else
begin
if(address[2:0] == 3'b000)
mem[8] <= write_data;
else if(address[2:0] == 3'b001)
mem[9] <= write_data;
else if(address[2:0] == 3'b010)
mem[10]<= write_data;
else if(address[2:0] == 3'b011)
mem[11]<= write_data;
else if(address[2:0] == 3'b100)
mem[12] <= write_data;
else if(address[2:0] == 3'b101)
mem[13] <= write_data;
else if(address[2:0] == 3'b110)
mem[14] <= write_data;
else
mem[15] <= write_data;
end
end
else
begin
mem[0] <= mem[0];
mem[1] <= mem[1];
mem[2] <= mem[2];
mem[3] <= mem[3];
mem[4] <= mem[4];
mem[5] <= mem[5];
mem[6] <= mem[6];
mem[7] <= mem[7];
mem[8] <= mem[8];
mem[9] <= mem[9];
mem[10]<= mem[10];
mem[11]<= mem[11];
mem[12]<= mem[12];
mem[13]<= mem[13];
mem[14]<= mem[14];
mem[15]<= mem[15];
end
end

always@(posedge clr,posedge clk)
if(clr)
read_data <= 16'b0;
else if(read_en == 1'b1)
begin
if(address[3] == 1'b0)
begin
if(address[2:0] == 3'b000)
read_data <= mem[0];
else if(address[2:0] == 3'b001)
read_data <= mem[1];
else if(address[2:0] == 3'b010)
read_data <= mem[2];
else if(address[2:0] == 3'b011)
read_data <= mem[3];
else if(address[2:0] == 3'b100)
read_data <= mem[4];
else if(address[2:0] == 3'b101)
read_data <= mem[5];
else if(address[2:0] == 3'b110)
read_data <= mem[6];
else if(address[2:0] == 3'b111)
read_data <= mem[7];
end
else
begin
if(address[2:0] == 3'b000)
read_data <= mem[8];
else if(address[2:0] == 3'b001)
read_data <= mem[9];
else if(address[2:0] == 3'b010)
read_data <= mem[10];
else if(address[2:0] == 3'b011)
read_data <= mem[11];
else if(address[2:0] == 3'b100)
read_data <= mem[12];
else if(address[2:0] == 3'b101)
read_data <= mem[13];
else if(address[2:0] == 3'b110)
read_data <= mem[14];
else
read_data <= mem[15];
end
end
else
read_data <= read_data;

endmodule

没有memory-partition的代码：

module memory(
clr, //reset
clk, //clock
address, //address for read or write
read_en, //read enable
write_en, //写使能
read_data, //读使能
write_data //写的数据
);

input wire clr; //reset
input wire clk; //clock
input wire [3:0]address; //address for read or write
input wire read_en; //read_enable signal
input wire write_en; //write_enable signal
output reg [15:0]read_data; //the data you read from the memory
input wire [15:0]write_data; //write data to memory

reg [15:0]mem[15:0]; //get a 16*16's memory

always@(posedge clr,posedge clk)
begin
if(clr)
begin
mem[0] <= 16'b0;
mem[1] <= 16'b0;
mem[2] <= 16'b0;
mem[3] <= 16'b0;
mem[4] <= 16'b0;
mem[5] <= 16'b0;
mem[6] <= 16'b0;
mem[7] <= 16'b0;
mem[8] <= 16'b0;
mem[9] <= 16'b0;
mem[10] <= 16'b0;
mem[11] <= 16'b0;
mem[12] <= 16'b0;
mem[13] <= 16'b0;
mem[14] <= 16'b0;
mem[15] <= 16'b0;
end
else if(write_en == 1'b1)
begin
if(address == 4'b0000)
mem[0] <= write_data;
else if(address == 4'b0001)
mem[1] <= write_data;
else if(address == 4'b0010)
mem[2] <= write_data;
else if(address == 4'b0011)
mem[3] <= write_data;
else if(address == 4'b0100)
mem[4] <= write_data;
else if(address == 4'b0101)
mem[5] <= write_data;
else if(address == 4'b0110)
mem[6] <= write_data;
else if(address == 4'b0111)
mem[7] <= write_data;
else if(address == 4'b1000)
mem[8] <= write_data;
else if(address == 4'b1001)
mem[9] <= write_data;
else if(address == 4'b1010)
mem[10]<= write_data;
else if(address == 4'b1011)
mem[11]<= write_data;
else if(address == 4'b1100)
mem[12] <= write_data;
else if(address == 4'b1101)
mem[13] <= write_data;
else if(address == 4'b1110)
mem[14] <= write_data;
else
mem[15] <= write_data;
end
else
begin
mem[0] <= mem[0];
mem[1] <= mem[1];
mem[2] <= mem[2];
mem[3] <= mem[3];
mem[4] <= mem[4];
mem[5] <= mem[5];
mem[6] <= mem[6];
mem[7] <= mem[7];
mem[8] <= mem[8];
mem[9] <= mem[9];
mem[10]<= mem[10];
mem[11]<= mem[11];
mem[12]<= mem[12];
mem[13]<= mem[13];
mem[14]<= mem[14];
mem[15]<= mem[15];
end
end

always@(posedge clr,posedge clk)
if(clr)
read_data <= 16'b0;
else if(read_en == 1'b1)
begin
if(address == 4'b0000)
read_data <= mem[0];
else if(address == 4'b0001)
read_data <= mem[1];
else if(address == 4'b0010)
read_data <= mem[2];
else if(address == 4'b0011)
read_data <= mem[3];
else if(address == 4'b0100)
read_data <= mem[4];
else if(address == 4'b0101)
read_data <= mem[5];
else if(address == 4'b0110)
read_data <= mem[6];
else if(address == 4'b0111)
read_data <= mem[7];
else if(address == 4'b1000)
read_data <= mem[8];
else if(address == 4'b1001)
read_data <= mem[9];
else if(address == 4'b1010)
read_data <= mem[10];
else if(address == 4'b1011)
read_data <= mem[11];
else if(address == 4'b1100)
read_data <= mem[12];
else if(address == 4'b1101)
read_data <= mem[13];
else if(address == 4'b1110)
read_data <= mem[14];
else
read_data <= mem[15];
end
else
read_data <= read_data;

endmodule

仿真代码：

module test;
// Inputs
reg clr;
reg clk;
reg [3:0] address;
reg read_en;
reg write_en;
reg [15:0] write_data;

// Outputs
wire [15:0] read_data;

// Instantiate the Unit Under Test (UUT)
memory uut (
.clr(clr),
.clk(clk),
.address(address),
.read_en(read_en),
.write_en(write_en),
.read_data(read_data),
.write_data(write_data)
);

`define gr0 4'b0000
`define gr1 4'b0001
`define gr2 4'b0010
`define gr3 4'b0011
`define gr4 4'b0100
`define gr5 4'b0101
`define gr6 4'b0110
`define gr7 4'b0111
`define gr8 4'b1000
`define gr9 4'b1001
`define gr10    4'b1010
`define gr11   4'b1011
`define gr12   4'b1100
`define gr13   4'b1101
`define gr14   4'b1110
`define gr15   4'b1111

always #50
clk = ~clk;
initial begin

$dumpfile("memory.vcd");
$dumpvars(1,test.uut);
$display("mem1: mem2: mem3: mem4: mem5: mem6: mem7: mem8: mem9:mem10:mem11:mem12:mem13:mem14:mem15");
$monitor("%h:%h:%h:%h:%h:%h:%h:%h:%h:%h:%h:%h:%h:%h:%h:%h",
uut.mem[`gr0], uut.mem[`gr1],uut.mem[`gr2], uut.mem[`gr3],uut.mem[`gr4],uut.mem[`gr5], uut.mem[`gr6],uut.mem[`gr7],
uut.mem[`gr8], uut.mem[`gr9],uut.mem[`gr10], uut.mem[`gr11],uut.mem[`gr12], uut.mem[`gr13],uut.mem[`gr14],uut.mem[`gr15]);

// Initialize Inputs
clr = 1;
clk = 0;
read_en = 0;
write_en = 0;
write_data = 0;
address = 0;
// Wait 100 ns for global reset to finish
#100;
write_en = 1;
clr = 0;
// Add stimulus here
#100;
address <= `gr0;
write_data <= 16'hffff;
#100;
address <= `gr1;
write_data <= 16'h00ff;
#100;
address <= `gr2;
write_data <= 16'hff00;
#100;
address <= `gr3;
write_data <= 16'h0ff0;
#100;
address <= `gr4;
write_data <= 16'hf000;
#100;
address <= `gr5;
write_data <= 16'h0f00;
#100;
address <= `gr6;
write_data <= 16'h00f0;
#100;
address <= `gr7;
write_data <= 16'h000f;
#100;
address <= `gr8;
write_data <= 16'hff00;
#100;
address <= `gr9;
write_data <= 16'hff11;
#100;
address <= `gr10;
write_data <= 16'h1234;
#100;
address <= `gr11;
write_data <= 16'hff11;
#100;
address <= `gr12;
write_data <= 16'hff00;
#100;
address <= `gr13;
write_data <= 16'h001f;
#100;
address <= `gr14;
write_data <= 16'hf111;
#100;
address <= `gr15;
write_data <= 16'habcd;
#100;
write_en <= 0;
read_en <= 1;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
write_en <= 1;
read_en <= 0;
#100;
address <= `gr0;
write_data <= 16'hffff;
#100;
address <= `gr1;
write_data <= 16'h00ff;
#100;
address <= `gr2;
write_data <= 16'hef00;
#100;
address <= `gr3;
write_data <= 16'hfff0;
#100;
address <= `gr4;
write_data <= 16'hf0f0;
#100;
address <= `gr5;
write_data <= 16'h0f00;
#100;
address <= `gr6;
write_data <= 16'h0ff0;
#100;
address <= `gr7;
write_data <= 16'h0002;
#100;
address <= `gr8;
write_data <= 16'hffff;
#100;
address <= `gr9;
write_data <= 16'h0000;
#100;
address <= `gr10;
write_data <= 16'hff34;
#100;
address <= `gr11;
write_data <= 16'hee11;
#100;
address <= `gr12;
write_data <= 16'hffe0;
#100;
address <= `gr13;
write_data <= 16'h0f1f;
#100;
address <= `gr14;
write_data <= 16'hff11;
#100;
address <= `gr15;
write_data <= 16'ha11d;
#100;
write_en <= 0;
read_en <= 1;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
write_en = 1;
clr = 0;
// Add stimulus here
#100;
address <= `gr0;
write_data <= 16'hffff;
#100;
address <= `gr1;
write_data <= 16'h00ff;
#100;
address <= `gr2;
write_data <= 16'hff00;
#100;
address <= `gr3;
write_data <= 16'h0ff0;
#100;
address <= `gr4;
write_data <= 16'hf000;
#100;
address <= `gr5;
write_data <= 16'h0f00;
#100;
address <= `gr6;
write_data <= 16'h00f0;
#100;
address <= `gr7;
write_data <= 16'h000f;
#100;
address <= `gr8;
write_data <= 16'hff00;
#100;
address <= `gr9;
write_data <= 16'hff11;
#100;
address <= `gr10;
write_data <= 16'h1234;
#100;
address <= `gr11;
write_data <= 16'hff11;
#100;
address <= `gr12;
write_data <= 16'hff00;
#100;
address <= `gr13;
write_data <= 16'h001f;
#100;
address <= `gr14;
write_data <= 16'hf111;
#100;
address <= `gr15;
write_data <= 16'habcd;

#100;
write_en <= 0;
read_en <= 1;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
write_en <= 1;
read_en <= 0;
#100;
address <= `gr0;
write_data <= 16'hffff;
#100;
address <= `gr1;
write_data <= 16'h00ff;
#100;
address <= `gr2;
write_data <= 16'hef00;
#100;
address <= `gr3;
write_data <= 16'hfff0;
#100;
address <= `gr4;
write_data <= 16'hf0f0;
#100;
address <= `gr5;
write_data <= 16'h0f00;
#100;
address <= `gr6;
write_data <= 16'h0ff0;
#100;
address <= `gr7;
write_data <= 16'h0002;
#100;
address <= `gr8;
write_data <= 16'hffff;
#100;
address <= `gr9;
write_data <= 16'h0000;
#100;
address <= `gr10;
write_data <= 16'hff34;
#100;
address <= `gr11;
write_data <= 16'hee11;
#100;
address <= `gr12;
write_data <= 16'hffe0;
#100;
address <= `gr13;
write_data <= 16'h0f1f;
#100;
address <= `gr14;
write_data <= 16'hff11;
#100;
address <= `gr15;
write_data <= 16'ha11d;
#100;
write_en <= 0;
read_en <= 1;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
write_en = 1;
clr = 0;
// Add stimulus here
#100;
address <= `gr0;
write_data <= 16'hffff;
#100;
address <= `gr1;
write_data <= 16'h00ff;
#100;
address <= `gr2;
write_data <= 16'hff00;
#100;
address <= `gr3;
write_data <= 16'h0ff0;
#100;
address <= `gr4;
write_data <= 16'hf000;
#100;
address <= `gr5;
write_data <= 16'h0f00;
#100;
address <= `gr6;
write_data <= 16'h00f0;
#100;
address <= `gr7;
write_data <= 16'h000f;
#100;
address <= `gr8;
write_data <= 16'hff00;
#100;
address <= `gr9;
write_data <= 16'hff11;
#100;
address <= `gr10;
write_data <= 16'h1234;
#100;
address <= `gr11;
write_data <= 16'hff11;
#100;
address <= `gr12;
write_data <= 16'hff00;
#100;
address <= `gr13;
write_data <= 16'h001f;
#100;
address <= `gr14;
write_data <= 16'hf111;
#100;
address <= `gr15;
write_data <= 16'habcd;

#100;
write_en <= 0;
read_en <= 1;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;

#100;
write_en <= 1;
read_en <= 0;
#100;
address <= `gr0;
write_data <= 16'hffff;
#100;
address <= `gr1;
write_data <= 16'h00ff;
#100;
address <= `gr2;
write_data <= 16'hef00;
#100;
address <= `gr3;
write_data <= 16'hfff0;
#100;
address <= `gr4;
write_data <= 16'hf0f0;
#100;
address <= `gr5;
write_data <= 16'h0f00;
#100;
address <= `gr6;
write_data <= 16'h0ff0;
#100;
address <= `gr7;
write_data <= 16'h0002;
#100;
address <= `gr8;
write_data <= 16'hffff;
#100;
address <= `gr9;
write_data <= 16'h0000;
#100;
address <= `gr10;
write_data <= 16'hff34;
#100;
address <= `gr11;
write_data <= 16'hee11;
#100;
address <= `gr12;
write_data <= 16'hffe0;
#100;
address <= `gr13;
write_data <= 16'h0f1f;
#100;
address <= `gr14;
write_data <= 16'hff11;
#100;
address <= `gr15;
write_data <= 16'ha11d;

#100;
write_en <= 0;
read_en <= 1;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
address <= `gr15;
#100;
address <= `gr14;
#100;
address <= `gr13;
#100;
address <= `gr12;
#100;
address <= `gr11;
#100;
address <= `gr10;
#100;
address <= `gr9;
#100;
address <= `gr8;
#100;
address <= `gr7;
#100;
address <= `gr6;
#100;
address <= `gr5;
#100;
address <= `gr4;
#100;
address <= `gr3;
#100;
address <= `gr2;
#100;
address <= `gr1;
#100;
address <= `gr0;
#100;
write_en = 1;
clr = 0;
// Add stimulus here
#100;
address <= `gr0;
write_data <= 16'hffff;
#100;
address <= `gr1;
write_data <= 16'h00ff;
#100;
address <= `gr2;
write_data <= 16'hff00;
#100;
address <= `gr3;
write_data <= 16'h0ff0;
#100;
address <= `gr4;
write_data <= 16'hf000;
#100;
address <= `gr5;
write_data <= 16'h0f00;
#100;
address <= `gr6;
write_data <= 16'h00f0;
#100;
address <= `gr7;
write_data <= 16'h000f;
#100;
address <= `gr8;
write_data <= 16'hff00;
#100;
address <= `gr9;
write_data <= 16'hff11;
#100;
address <= `gr10;
write_data <= 16'h1234;