网络控制晶片分类

以DAVICOM公司网络控制晶片为例进行说明。

 

上面的芯片分类，是我学习了DAVICOM官网之后，自己画的图。可以了解一下。

我们做嵌入式开发的时候，会使用到网卡，那我们会根据主MCU和一些条件去选择网卡芯片，上面的芯片都是网卡芯片，如何选择啦？

 

1.  ETHERNET CONTROLLERS

ETHERNETCONTROLLERS(以太网控制器)，此类别的网卡芯片是网卡控制器。

a.    TheDM9051(I) is a fully integrated and cost-effective low pin count single chipFast Ethernet controller with a Serial Peripheral Interface (SPI), a 10/100MPHY and MAC, and 16K-byte SRAM.(DM9051（I）是一款完全集成且经济高效的低引脚数单芯片快速以太网控制器，串行外设接口（SPI），10 / 100M PHY和MAC以及16K字节SRAM。)

 

Block Diagram：

Processor Interface :  SPI

b.    TheDM9000 is a fully integrated and cost-effective single chip Fast Ethernet MAC

controller with a general processor interface, a 10/100M PHY and4K Dword SRAM. (DM9000是一款完全集成且经济高效的单芯片快速以太网MAC

带有通用处理器接口的控制器，10 / 100M PHY和4K Dword SRAM。)

 

Block Diagram：

The DM9000 also provides a MII interface to connect HPNA deviceor other transceivers that support MII interface. The DM9000 supports 8-bit,16-bit and 32-bit uP interfaces to internal memory accesses for differentprocessors.

 

processor interface: byte/word/dword of I/O command to internalmemory data operation

c.    TheDM9102D is a fully integrated and cost effective single chip Fast Ethernet NIC controller.

The DM9102D provides direct interface to the PCI bus andsupports bus master mode to achieve the high performance of the PCI bus. Itfully complies with PCI 2.2.

 

Integrated Fast Ethernet MAC, Physical Layer and transceiver inone chip.

Block Diagram：

Interface : PCI.

 

小结：看Block Diagram和说明可知：DM9051，DM9000， DM9102D三款芯片的共同点是MAC + PHY。即这款芯片有PHY收发器也有MAC传输层控制器。不同点是，和MCU传输数据的时候，接口有差异，分别为SPI, NON PCI, PCI。

2.  PHY

a.    TheDM9161EP is a physical layer, single-chip, and low power transceiver for100BASE-TX 100BASE-FX and 10BASE-T operations.( DM9161EP是用于100BASE-TX 100BASE-FX和10BASE-T操作的物理层，单芯片和低功耗收发器。)

Through the Media Independent Interface (MII), the DM9161EPconnects to the Medium Access Control (MAC) layer, ensuring a highinter-operability from different vendors.( 通过媒体独立接口（MII），DM9161EP连接到媒体访问控制（MAC）层,确保不同的互操作性供应商。)

 

The DM9161EP uses a low power and high performance CMOS process.It contains the entire physical layer functions of 100BASE-TX as defined byIEEE802.3u, including the Physical Coding Sublayer (PCS), Physical MediumAttachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD),10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit(TPMAU). The DM9161EP provides a strong support for the auto-negotiationfunction, utilizing automatic media speed and protocol selection. Furthermore,due to the built-in wave-shaping filter, the DM9161EP needs no external filterto transport signals to the media in 100MBASE-TX or 10MBASE-T Ethernetoperation.( DM9161EP采用低功耗和高性能CMOS工艺。 它包含IEEE802.3u定义的100BASE-TX的全部物理层功能，包括物理编码子层（PCS），物理媒体附件（PMA），双绞线物理介质相关子层（TP-PMD），10BASE-TX编码器/解码器（ENC/ DEC）和双绞线媒体访问单元（TPMAU）。该DM9161EP为自动协商功能提供强有力的支持自动媒体速度和协议选择。此外，由于内置波形整形滤波器，DM9161EP不需要外部滤波器来传输信号媒体采用100MBASE-TX或10MBASE-T以太网操作)

Block Diagram：

interface : MII or RMII (Reduced MII) interface, at he 100BASE-TX

interface :  GPSI (7-Wired) or MII mode at the 10Base-T

 

小结：此类芯片只是一个PHY收发器，属性是物理层收发器，DM9161AEP通过可变电压的 MII 或 RMII 标准数字接口连接到 MAC 层，别的芯片提供MAC层。此类芯片选择主mcu的时候，主mcu必须有MAC控制器。例如：S3C2510(内部含有MAC接口)+DM9161。STM32F4+LAN8720A组合，IMX6+BCM54811也是类似的选择。

在应用过程中，DM9161AEP常出现的错误是，晶振的连接，以及网络变压器的匹配，所以应该慎重选择。ETHERNET CONTROLLERS类芯片是PHY+MAC一体的，

ETHERNET CONTROLLERS类芯片是将以太网媒体接入控制器(MAC)和物理接口收发器(PHY)整合进同一芯片，它包含OSI七层参考模型中第二层数据链路层（MAC）和第一层物理层（PHY）。这样能去掉许多外接元器件。这种方案可使MAC和PHY实现很好的匹配，同时还可减小引脚数、缩小芯片面积；DM9161是物理层接口收发器（PHY），其只包含OSI七层参考模型中的第一层物理层（PHY）。

如果要详细了解此类芯片的使用，可是看STM32F4开发指南-寄存器版本_V1.1里的第 六十章网络通信。

3.  SWITCH

The DM8603 is Davicom’s new fully integratedthree-port 10M/100Mbps Fast Ethernet Controller

with Fiber interface. As a fast Ethernet switch,the DM8603 consists of two PHY ports and a third

port with either MII or RMII interface. As theDM8603 was designed with our customers’

requirements in mind, the switch is optimized forhigh performance while being highly

cost-effective.

The two PHY ports on the DM8603 are IEEE 802.3ustandards compliant. Aside for the first two

PHY ports and in an effort for maximum applicationflexibility, the third port on the DM8603 offers

the options to either connect with an MII, reversedMII, or RMII. The reversed MII configuration is

used to connect with SoC’s with a MII interface.The RMII interface is the alternative interface

configuration in case of the need to connect alower pin count Ethernet PHY or SoC.

To maximize the performance of each port, theDM8603 was designed with a number of

features. For proper bandwidth, each port alsosupports ingress and/or egress rate control. In

support of efficient packet forwarding, the DM8603has port-based VLAN with tag/un-tag functions

for up to 16 groups of 802.1Q. Each port includesMIB counters, loop-back capability, built in

memory self test (BIST) for the system, and boardlevel diagnostic.

In designing for the requirements of various data,voice, and video applications, enough internal

memory has been provided for usage of the DM8603’sthree ports, and the internal memory

supports up to 1K uni-cast MAC address table. Thento meet the demands of various bandwidth

and latency issues in data, voice, and videoapplications, each port of the DM8603 has four priority

transmit queues. These queues can be defined eitherthrough port-based operation, 802.1p

VLAN, or the IP packet TOS field automatically.

Block Diagram：

 

4.  USB TO ETHERNET

The DM9620/21 USB to 10/100Mbps Fast Ethernetcontroller is a high performance and highly

integrated ASIC with embedded SSRAM for packetbuffering. It enables low cost and

affordable Fast Ethernet network connection todesktop, notebook PC, and embedded system

using popular USB ports.

It has an USB interface to communicate with USBhost controller and is compliant with USB

specification V1.0, V1.1 and V2.0. It implements10/100Mbps Ethernet LAN function based on

IEEE802.3, and IEEE802.3u standards.

DM9620/21 integrates an on-chip 10/100Mbps EthernetPHY to simplify system design and

provides an optional media-independent interface(MII/RMII/Rev_MII).

Block Diagram：

Certification :

实物：