verilog HDLBits刷题[Counters]“Count10”---Decade counter

一、题目Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.Module Declarationmodule top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q);二、分析在上一个题目中4bit计数器计数从0-15记满16个数后计数器会自动从0开始计数。而在本题中计数周期为10从0-9记满10个数计数器不会自动清零故需要一个判断语句判断是否记满10个数记满则清零三、代码实现module top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q); reg [3:0]cnt; always(posedge clk) if(reset) cnt4d0; else if(cnt4d9) cnt4d0; else cntcnt4d1; assign qcnt; endmodule 或者 module top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q); reg [3:0]cnt; always(posedge clk)begin if(reset|cnt4d9) cnt4d0; else cntcnt4d1; end assign qcnt; endmodulemodule top_module( input clk, input reset, output reg [3:0] q); always (posedge clk) if (reset || q 9) // Count to 10 requires rolling over 9-0 instead of the more natural 15-0 q 0; else q q1; endmodule四、时序